Digital systems and the semiconductor devices or integrated circuits (ICs) that invariably make up the systems are continuing to evolve and become more and more complex. Concomitant with the increase in complexity is a decrease in the use of or strict adherence to a uniform, chip-wide or system-wide clock signal. Instead, clock signal distribution delays and related non-deterministic signal-to-clock skews inherent in large, complex systems and integrated circuits (ICs) are often accounted for in the design of the IC or system. During the development of such systems, tolerance for the expected and non-deterministic delays and skews is simply ‘built-in’ to the system design. This built-in tolerance enables the systems to operate properly in the presence of the delays and skews.
For example, in some large ICs, a signal distribution bus may include a clock signal line or a strobe line that is routed along with the data lines of the bus thereby insuring that data and clock or strobe experience similar time delays. Routing of a strobe along with the data is sometimes referred to as a source synchronous bus design. In source synchronous bus designs, local subsystems on the IC derive clock signals or timing information from the bus clock signal(s) or strobe. Thus, the individual subsystems are often poorly synchronized relative to the master clock but are largely immune in an operational sense to the delay effects of the data bus routing. Differential processing delays within individual subsystems of an IC also often can be accounted for with this approach by allowing the subsystems to generate strobes to signal to other subsystems that valid data has been placed on the bus.
In other instances of design methodologies for large ICs and systems that attempt to minimize the operational effects of delays and skews, timing and/or bit level synchronization is provided by or embedded in the data itself. An example of this approach is found in so-called asynchronous serial communications channels such as RS-232C. In instances where timing information is provided by or embedded in the data, the subsystems derive a local clock from the data as it arrives at the subsystem. The effect of non-deterministic, time varying skews experienced by the data is thereby rendered essentially irrelevant because the receiver's clock recovery circuit tracks the skew. Among the causes of non-deterministic skews are temperature variations during operation.
Furthermore, in some complex systems and ICs multiple clocks with varying clock rates are employed. The use of multiple clocks in an IC is often referred to as a multiple clock domain IC. The use of multiple clocks in an IC can cause non-deterministic behavior at the bit level. Again, the system or IC design takes into account the potential for non-deterministic bit-level performance enabling proper operation. Moreover, even when a common clock is used throughout an IC or system, modern complex ICs are often designed to tolerate and even expect relatively large differences or ‘skews’ between clock signals at various points within the IC.
The presence of non-deterministic skews and chips designed to tolerate large skews combined with market pressures for lower IC and system costs result in a need for incorporating tolerance to a range of skews into an IC design and test. In the end, the trend is that as complexity increases, the ICs and the systems that use them are tending to exhibit an overall decrease in the phase relationship between the chip-wide or system-wide clock and the digital data generated by these ICs and systems.
The trend toward decreasing tightness or loosening of the phase relationships between data and clock can and does create significant problems for the testing of devices and systems. These problems are often most apparent when testing modern systems and ICs using automated test equipment (ATE). However, testing with other means can also be adversely effected by the reduced phase relationship between data and clock. In the worst case, the test system will fail devices that are actually functioning according to the design specifications simply because the test system incorrectly accounted for the reduced tightness of the data/clock phase relationship of the device under test (DUT).
To better understand how clock skews and clock delays can pose a problem for conventional testing using ATEs and related test systems consider that during operation an ATE typically generates a chip-wide, common clock signal along with one or more analog and/or digital waveforms that act as input data. The input data is applied to inputs of the device under test (DUT). The DUT processes the data and generates output data that is sampled by the ATE using the master clock. The sampled data typically are compared to expected data to determine whether or not the device is operating properly and to verify that the device meets the specifications.
Conventionally, the ATE attempts to accurately strobe or sample the output data at a beginning and ending time window in which a given logic level output is expected. When the strobed logic level is not as expected, the conclusion is that either a timing error or a bit error has occurred. To resolve whether the error is timing related or bit related, expected levels must generally be known. In short, there is usually no explicit separation between bit level test and timing test in conventional testing systems and methodologies.
Unfortunately, as the non-deterministic/non-repeatable skew increases between the DUT output data and the common clock due to variations of the internal clock distribution and processing delays within the DUT, the validity of the sampled data collected by the ATE tends to decrease. Higher clock speeds only exacerbate the situation by reducing the sample period used by the ATE. Ultimately, the skew can become so severe that the ATE will consistently fail a properly functioning DUT. Even before the skew level has become severe enough for a complete breakdown in the ATE capability to differentiate operational and non-operational DUTs, the skew that may be tolerable in normal DUT operation can cause the ATE to intermittently fail DUTs, leading to a decrease in manufacturing yield and an increase in IC cost.
Several techniques are used to mitigate the effects of clock skew with respect to automated testing. In one technique, the same test of a given DUT is performed multiple times with a fixed, chip-wide clock. The clock is used as a sampling frequency establishing the sample time within each clock period at which the data output by the DUT is sampled or measured. Alternatively, the sampling of output data is performed at various different sample times within a clock period in each of several successive tests. The goal is to get at least one valid sample of each output data bit regardless of the phase relationship between the DUT clock and the sample time. The error maps generated during each of the multiple tests are examined to determine if all test vectors have passed all signals at least once during the series of multiple tests. Note that it is not generally sufficient that a first bit passes a first test vector while a second bit passes in a second test vector. Typically, both bits must pass in the same vector so to verify cross-pin timing. Among the disadvantages of this technique are long test times, fast overflow of the error maps used by the test equipment, and difficulty handling multi-period phase deviations.
In another technique, applicable primarily to the source synchronous bus and multiple clock domain situations, an application specific resynchronization circuit is used on the DUT interface board. The resynchronization circuit attempts to correct for any kind of skew between the ATE generated master clock and the sampled data generated by the DUT. Among the problems with using an application-specific resynchronization circuit on the DUT interface board is that it can reduce the reliability of the DUT interface board and introduce signal integrity problems due to the need for by-pass relays for timing tests and the DC parametric test. In addition, the use of an application-specific resynchronization circuit requires additional effort associated with the design of such a circuit. A related alternative technique to using an application-specific resynchronization circuit on the DUT board is to integrate a resynchronization circuit into the ATE that is as generic as possible. However, it is difficult, if not impossible, to develop a really ‘generic’ circuit that can handle not only all of the currently employed clocking schemes, but also accommodate future schemes.
Finally, in certain situations such as testing serial communication channels in which the bit timing is embedded in the data, a circuit added to either the DUT interface board or the ATE can be used to extract the timing information in much the same manner as is done by the communication channel devices themselves. This sort of circuit is often called a clock recovery or clock synchronization circuit. The main disadvantage of this sort of approach is that this approach is fairly specific to the type of embedded bit timing that is being employed and so there is considerable difficulty associated with designing a sufficiently generic clock recovery circuit, especially if the circuit is to be added to the ATE. In addition, in the presence of a marginally faulty DUT, the clock recovery circuit itself might not work reliably enough to definitively determine whether the DUT is faulty or not.
Accordingly, it would be advantageous to have a method and apparatus for testing devices using an ATE or related test system that makes the test system insensitive to so-called ‘tolerable’ skews, especially non-deterministic skews or drifts, between the testing system master clock and the output data or signal under test that is generated by the DUT. The ability of the test system to accommodate tolerable skews should be accompanied by an ability to flag skews that are considered too large based on the DUT design specifications. In addition, it would be desirable that such a method and apparatus be fairly generic in terms of covering a large variety of clocking protocols and applicable to a variety of test/analysis methodologies, including but not limited to, analysis of digital signals using ATE, verification tools, digital stimulus and response systems, and logic analyzers. Further, it would be desirable that the method and apparatus be applicable to tests ranging from chip-level to systems level testing. Such a method and apparatus would solve a long-standing need for complex digital IC and system testing.